An IC layout specifies portions of various components of an IC. When the IC is to include a large number of registers, latches, flip-flops and/or other types of clocked devices (“sinks”) that are to be clocked by one or more clocks, the IC must include one or more clock trees for delivering the clock signal from the clock source to all of the sinks to be clocked by it. A clock tree distributes a clock signal from its root to a set of sinks within an IC through a branching network of fan-out buffers. A clock tree includes a hierarchy of fan-out buffers, clock gating elements, and clock logic, collectively referred to as clock drivers (which may or may not invert the clock signal), for fanning the clock tree out from one or more buffers at a top level of the hierarchy to a large number of buffers, or clock gating elements, or clock logic at the lowest level of the hierarchy, that drive the clock inputs of the sinks. Conventional techniques for constructing the branching network of fan-out clock drivers to the sinks assume a single unique location or point for each clock driver. However, these conventional techniques are sub-optimal for trunk-level clustering because they lead to increased gate count, gate area, and routing resource usage.